MediaStation 5000: Integrating Video and Audio
IEEE MultiMedia
On-line Multioperand Addition Based on On-line Full Adders
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Performance comparison of the emerging H.264 video coding standard with the existing standards
ICME '03 Proceedings of the 2003 International Conference on Multimedia and Expo - Volume 2
An efficient VLSI architecture for H.264 variable block size motion estimation
IEEE Transactions on Consumer Electronics
A new diamond search algorithm for fast block-matching motion estimation
IEEE Transactions on Image Processing
Vector Processing as a Soft Processor Accelerator
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Exploration of hardware sharing for image encoders
Proceedings of the Conference on Design, Automation and Test in Europe
High-Speed, SAD Based Wavefront Sensor Architecture Implementation on FPGA
Journal of Signal Processing Systems
Reconfigurable architecture for VBSME with variable pixel precision
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Bit-by-Bit Pipelined and Hybrid-Grained 2D Architecture for Motion Estimation of H.264/AVC
Journal of Signal Processing Systems
A Low Cost Architecture for Variable Block Size Motion Estimation
Journal of Signal Processing Systems
Analysis and Design of Low-Cost Bit-Serial Architectures for Motion Estimation in H.264/AVC
Journal of Signal Processing Systems
An Adaptive Motion Estimation Architecture for H.264/AVC
Journal of Signal Processing Systems
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H.264/AVC is the latest video coding standard adopting variable block size motion estimation (VBS-ME), quarter-pixel accuracy, motion vector prediction and multi-reference frames for motion estimation. These new features result in much higher computation requirements than previous coding standards. In this paper we propose a novel most significant bit (MSB) first bit-serial architecture for full-search block matching VBS-ME, and compare it with systolic implementations. Since the nature of MSB-first processing enables early termination of the sum of absolute difference (SAD) calculation, the average hardware performance can be enhanced. Five different designs, one and two dimensional systolic and tree implementations along with bit-serial, are compared in terms of performance, pixel memory bandwidth, occupied area and power consumption.