Motion estimation performance of the TM3270 processor
Proceedings of the 2005 ACM symposium on Applied computing
Algorithms and DSP implementation of H.264/AVC
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Efficient Motion Estimation Algorithm for Advanced Video Coding
ICCIMA '07 Proceedings of the International Conference on Computational Intelligence and Multimedia Applications (ICCIMA 2007) - Volume 03
Integer-pixel motion estimation H.264/AVC accelerator architecture with optimal memory management
Microprocessors & Microsystems
A new diamond search algorithm for fast block-matching motion estimation
IEEE Transactions on Image Processing
Hexagon-based search pattern for fast block motion estimation
IEEE Transactions on Circuits and Systems for Video Technology
Overview of the H.264/AVC video coding standard
IEEE Transactions on Circuits and Systems for Video Technology
Rate-constrained coder control and comparison of video coding standards
IEEE Transactions on Circuits and Systems for Video Technology
Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder
IEEE Transactions on Circuits and Systems for Video Technology
Improvements on Fast Motion Estimation Strategy for H.264/AVC
IEEE Transactions on Circuits and Systems for Video Technology
| Hi-index | 0.00 |
A hardware oriented Motion Estimation (ME) algorithm which can be combined into FPGA based SDTV or HDTV encoder is proposed. The present Full Search (FS) algorithm cost too much logic resource, thus it limits the application of real time video encoder. And all of the fast algorithms are difficult to reuse data between candidates, thus they are not suitable for ASIC or FPGA implementation. After reviewing the previous ME algorithms and researching the distribution of Motion Vector (MV), we optimize the hardware ME by selecting block-matching candidates in the Search Window (SW). Then a novel Big-Hexagon-Like searching route is proposed. And the number of PE arrays is decreased from 8 to 2. Therefore, the high logic resource cost of ME is alleviated notably. And the method of data reusing is also proposed. Then a hardware architecture is proposed. We have tested the proposal with High definition, CIF and QCIF video sequences. Comparing the test result with F017 and Diamond algorithms, the proposal has a comparative RDO (Rate-Distortion Optimization) performance to F017 and is better than Diamond which is adopted by T264. An FPGA implementation of the proposed algorithm is realized, the result of implementation shows that the equivalent gates count is reduced to 121K.