Integer-pixel motion estimation H.264/AVC accelerator architecture with optimal memory management

Authors:
Armando Mora Campos;Francisco J. Ballester Merelo;Marcos A. Martínez Peiró;José A. Canals Esteve
Affiliations:
Department of Electrical and Electronic Engineering, Instituto Tecnológico de Querétaro, Querétaro 76000, Mexico;Department of Electronic Engineering, Universidad Politécnica de Valencia, Valencia 46022, Spain;Department of Electronic Engineering, Universidad Politécnica de Valencia, Valencia 46022, Spain;Department of Electronic Engineering, Universidad Politécnica de Valencia, Valencia 46022, Spain
Venue:
Microprocessors & Microsystems
Year:
2008

Citing 4
Cited 2

Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation

Algorithms, Complexity Analysis and VLSI Architectures for MPEG-4 Motion Estimation
Efficient and configurable full-search block-matching processors

IEEE Transactions on Circuits and Systems for Video Technology
Introduction to the special issue on the H.264/AVC video coding standard

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Rate-constrained coder control and comparison of video coding standards

IEEE Transactions on Circuits and Systems for Video Technology

A low cost hardware oriented motion estimation algorithm for HDTV

Proceedings of the first ACM/SIGEVO Summit on Genetic and Evolutionary Computation
Computation and power reduction techniques for H.264 intra prediction

Microprocessors & Microsystems

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Abstract

This paper presents an improved accelerator core for H.264/AVC video-coding motion estimation. The proposed hardware architecture meets the integer-pixel, full-search block-matching algorithm requirements with an optimal memory management and an effective data-path. Performance characteristics like low latency, high processing speed and efficiency near 100% are achieved without a high control overhead. The core calculates the 41 best motion vectors using a pipeline process. It is composed of a systolic 16x16 processor elements array, a sum of absolute differences adder tree and a Lagrangian rate/distortion cost optimizer. Implementation results based on FPGA devices in a system on chip (SoC) structure using VHDL are included.