A Mapping Strategy for Resource-Efficient Network Processing on Multiprocessor SoCs

  • Authors:
  • Matthias Grünewald;Jörg-Christian Niemann;Mario Porrmann;Ulrich Rückert

  • Affiliations:
  • -;-;-;-

  • Venue:
  • Proceedings of the conference on Design, automation and test in Europe - Volume 2
  • Year:
  • 2004

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Abstract

Hardware architectures based on a field of hardware-extended processors can provide flexible computing power for applications where parallelism can be exploited. For multiprocessors, the assignment of functionality to execution units can have a great impact on the performance.Additionally, finding the optimal mapping can be a time-consuming task. We present a multiprocessor architecture along with a suitable design method that includes an automatedsolution to the mapping problem. Our hardware architecture employs a network-on-chip (NoC) to achieve a high degree of scalability for the application and for the system in respect to future integration technologies.We also show how to reduce the packet buffer requirements with a proper scheduling strategy and present first estimates for the resource consumption of an application targeted for mobile networking.