Reconfigurable interconnect for next generation systems
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Networks on Silicon: Combining Best-Effort and Guaranteed Services
Proceedings of the conference on Design, automation and test in Europe
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Placement and Routing in 3D Integrated Circuits
IEEE Design & Test
Design of an interconnect architecture and signaling technology for parallelism in communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Read-proof hardware from protective coatings
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
A qualitative security analysis of a new class of 3-d integrated crypto co-processors
Cryptography and Security
Breaking and entering through the silicon
Proceedings of the 2013 ACM SIGSAC conference on Computer & communications security
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3D integration is a promising advanced manufacturing process offering a variety of new hardware security protection opportunities. This paper presents a way of securing 3D ICs using Hamiltonian paths as hardware integrity verification sensors. As 3D integration consists in the stacking of many metal layers, one can consider surrounding a security-sensitive circuit part by a wire cage. After exploring and comparing different cage construction strategies (and reporting preliminary implementation results on silicon), we introduce a "hardware canary". The canary is a spatially distributed chain of functions Fi positioned at the vertices of a 3D cage surrounding a protected circuit. A correct answer (Fn∘…∘F1)(m) to a challenge m attests the canary's integrity.