Digital communications: fundamentals and applications
Digital communications: fundamentals and applications
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Reconfigurable interconnect for next generation systems
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Data Communications and Networking
Data Communications and Networking
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
Handbook Of Digital Techniques For High-speed Design
Handbook Of Digital Techniques For High-speed Design
Low-power network-on-chip for high-performance SoC design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
RapidIO: The Embedded System Interconnect
RapidIO: The Embedded System Interconnect
Computer Organization and Architecture: Designing for Performance (7th Edition)
Computer Organization and Architecture: Designing for Performance (7th Edition)
Electro-Optical DSP of Tera Operations per Second and Beyond (Extended Abstract)
OSC '08 Proceedings of the 1st international workshop on Optical SuperComputing
A design space exploration of transmission-line links for on-chip interconnect
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
A new power-efficient CDMA-based transmitter for high-speed serial links
Analog Integrated Circuits and Signal Processing
CHES'12 Proceedings of the 14th international conference on Cryptographic Hardware and Embedded Systems
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The need for efficient interconnect architectures beyond the conventional time-division multiplexing (TDM) protocol-based interconnects has been brought on by the continued increase of required communication bandwidth and concurrency of small-scale digital systems. To improve the overall system performance without increasing communication resources and complexity, this paper presents a cost-effective interconnect architecture, communication protocol, and signaling technology that exploits parallelism in board-level communication, resulting in shorter latency and higher concurrency on a shared bus or link: the proposed source synchronous CDMA interconnect (SS-CDMA-I) enables dual concurrent transactions on a single wire line as well as flexible input/output (I/O) reconfiguration. The SS-CDMA-I utilizes 2-bit orthogonal CDMA coding and a variation of source synchronous clocking for multilevel superposition; a single 3-level SSCDMA-I line operates as if it consists of dual virtual time-multiplexed interconnects, which exploits communication parallelism with a reduced number of pins, wires, and complexity. The unique multiple access capability of the SSCDMA-I improves real-time communication between multiple semiconductor intellectual property (IP) blocks on a shared link or bus by reducing the bus contention interference from simultaneous traffic requests and by taking advantage of shorter request latency. The prototype transceiver chip is implemented in 0.18-µm CMOS and the 10-cm test PC board system achieves an aggregate data rate of 2.5 Gb/s/pin between four off-chip (2Tx-to-2Rx) I/Os.