Post-silicon validation opportunities, challenges and recent advances
Proceedings of the 47th Design Automation Conference
Optimized self-tuning for circuit aging
Proceedings of the Conference on Design, Automation and Test in Europe
Design techniques for cross-layer resilience
Proceedings of the Conference on Design, Automation and Test in Europe
Cross-layer resilience challenges: metrics and optimization
Proceedings of the Conference on Design, Automation and Test in Europe
Energy and reliability oriented mapping for regular Networks-on-Chip
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Cross-layer error resilience for robust systems
Proceedings of the International Conference on Computer-Aided Design
Using implications to choose tests through suspect fault identification
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
A dynamic self-adaptive correction method for error resilient application
Proceedings of the Conference on Design, Automation and Test in Europe
A failure prediction strategy for transistor aging
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Editor's note:The prospect of system failure has increased because of device- and chip-level effects in the late CMOS era, such as early-life failure and NBTI. In this article, the authors present novel system-level architecture and design innovations to cope with these lifetime reliability challenges.—Pradip Bose, IBM Research