Memory block based scan-BIST architecture for application-dependent FPGA testing

Authors:
Keita Ito;Tomokazu Yoneda;Yuta Yamato;Kazumi Hatayama;Michiko Inoue
Affiliations:
Nara Institute of Science and Technology, Nara, Japan;Nara Institute of Science and Technology, Nara, Japan;Nara Institute of Science and Technology, Nara, Japan;Nara Institute of Science and Technology, Nara, Japan;Nara Institute of Science and Technology, Nara, Japan
Venue:
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
Year:
2014

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Abstract

This paper presents a scan-based BIST architecture for FPGAs used as application-specific embedded devices for low-volume products. The proposed architecture efficiently utilizes memory blocks, instead of logic elements, to build up BIST components such as LFSR, MISR and scan chains for test points. It also provides enhanced scan functionality for test points and performs a hybrid test application of LOC and enhanced scan to improve delay test quality. Experimental results show that the proposed BIST architecture achieves high delay test quality with efficient resource utilization.