Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Weak Write Test Mode: An SRAM Cell Stability Design for Test Technique
Proceedings of the IEEE International Test Conference
Detection of SRAM cell stability by lowering array supply voltage
ATS '00 Proceedings of the 9th Asian Test Symposium
Testing for Resistive Opens and Stuck Opens
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Dynamic Read Destructive Fault in Embedded-SRAMs: Analysis and March Test Solution
ETS '04 Proceedings of the European Test Symposium, Ninth IEEE
AN SRAM WEAK CELL FAULT MODEL AND A DFT TECHNIQUE WITH A PROGRAMMABLE DETECTION THRESHOLD
ITC '04 Proceedings of the International Test Conference on International Test Conference
Impact of NBTI on SRAM Read Stability and Design for Reliability
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
MECCA: a robust low-overhead PUF using embedded memory array
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
Detecting stability faults in sub-threshold SRAMs
Proceedings of the International Conference on Computer-Aided Design
Testing methodology of embedded DRAMs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
Core-cell stability represents the ability of the core-cell to keep the stored data. With the rapid development of semiconductor memories, their test is becoming a major concern in VDSM technologies. It provides information about the SRAM design reliability, and its effectiveness is therefore mandatory for safety applications. Existing core-cell stability Design-for-Test (DfT) techniques consist in controlling the voltage levels of bit lines to apply a weak write stress on the core-cell under test. If the core-cell is weak, the weak write stress induces the faulty swap of the core-cell. However, these solutions are costly in terms of area and test application time, and generally require modifications of critical parts of the SRAM (core-cell array and/or the structure generating the internal auto-timing). In this paper, we present a new DfT technique for stability fault detection. It consists in modulating the word line activation in order to perform an adjustable weak write stress on the targeted core-cell for stability fault detection. Compared to existing DfT solutions, the proposed technique offers many advantages: programmability, low area overhead, low test application time. Moreover, it does not require any modification of critical parts of the SRAM.