Efficiently supporting fault-tolerance in FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Error detection for adaptive computing architectures in spacecraft applications
ACSAC '01 Proceedings of the 6th Australasian conference on Computer systems architecture
Designing fault tolerant systems into SRAM-based FPGAs
Proceedings of the 40th annual Design Automation Conference
Designing Fault-Tolerant Techniques for SRAM-Based FPGAs
IEEE Design & Test
A low-cost fault tolerant solution targeting commercial FPGA devices
Journal of Systems Architecture: the EUROMICRO Journal
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As field programmable gate arrays find increasing use in aerospace and terrestrial applications, a number of methods of fault tolerance have been developed to ensure reliable operation. Most current techniques output the required circuit area based on the desired level of fault tolerance with some techniques increasing the area by over 200%. In deployed systems, however, the FPGA is fixed and the area available for adding fault tolerance is limited. As a consequence, protecting an updated, larger circuit using the same fault tolerance scheme may result in a design that no longer fits in the deployed FPGA. This situation dictates the need for techniques that can trade fault tolerance for lower area penalties. Area constrained approaches accept available hardware resources as an input and outputs a partially fault tolerant circuit. The open question with these approaches is selecting the circuit subset to protect which will maximize the fault coverage. This paper presents several methodologies for selecting subsets and analyzes their performances on several circuits based on fault coverage provided and additional delay.