A low-cost fault tolerant solution targeting commercial FPGA devices
Journal of Systems Architecture: the EUROMICRO Journal
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The realization of embedded systems for safety critical applications as Custom embedded SoCs (System on Chip) realized on FPGAs (Field Programmable Gate Array) and hybrid SoCs including both custom ASIC cores, and programmable FPGA is nowadays rapidly increasing. In recent years, fault tolerance solutions for such systems have been developed and today are still addressed by ongoing research. More recently the application of FPGA partial dynamic reconfiguration capabilities to systems fault tolerance has been investigated and demonstrated by many fresh works, but primarily from an hardware perspective. In this paper a software framework for managing dynamic partial reconfiguration is proposed. Such framework is responsible of managing the replacement of faulty hardware peripherals with soft-core versions running on reconfigurable hardware areas allowing the software applications to be unaware of the underlying fault detection and reconfiguration process.