Microprocessor based testing for core-based system on chip
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
The Test Access Port and Boundary-Scan Architecture
The Test Access Port and Boundary-Scan Architecture
ITC '98 Proceedings of the 1998 IEEE International Test Conference
DEFUSE: A Deterministic Functional Self-Test Methodology for Processors
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Native Mode Functional Self-Test Generation for Systems-on-Chip
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
Software-Based Weighted Random Testing for IP Cores in Bus-Based Programmable SoCs
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
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We report on a new, reconfigurable, packet-based, embedded test protocol that supports several popular test methodologies (boundary scan, full-scan and BIST among others) for testing multi-core SOCs. Unlike the conventional SOC test methods that require use of an expensive automatic test equipment, our proposal uses on-chip embedded cores that serve as microtesters. The protocol is implemented using two embedded cores: Test Server and Test Client. The Test Server delivers test parameters as test packets to Test Clients. Experimental results show that our new test protocol can be implemented with low (less than 2%) hardware overhead. Since hardware overhead for our test protocol does not grow as the size of SOCs, it will be even lower for large SOCs.