Instruction-level DFT for testing processor and IP cores in system-on-a-chip
Proceedings of the 38th annual Design Automation Conference
Embedded software-based self-testing for SoC design
Proceedings of the 39th annual Design Automation Conference
Journal of Electronic Testing: Theory and Applications
Embedded Software-Based Self-Test for Programmable Core-Based Designs
IEEE Design & Test
Re-configurable embedded core test protocol
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Reducing test time with processor reuse in network-on-chip based systems
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
On reliable modular testing with vulnerable test access mechanisms
Proceedings of the 45th annual Design Automation Conference
Scheduling Power-Constrained Tests through the SoC Functional Bus
IEICE - Transactions on Information and Systems
Functional processor-based testing of communication peripherals in systems-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism
Journal of Electronic Testing: Theory and Applications
On-chip SOC test platform design biased on IEEE 1500 standard
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Software-Based Testing for System Peripherals
Journal of Electronic Testing: Theory and Applications
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We present a novel test methodology for testing IP cores in SoCs with embedded processor cores. A test program is run on the processor core that generates and delivers test patterns to the target IP cores in the SoC and analyzes the test responses. This provides tremendous flexibility in the type of patterns that can be applied to the IP cores without incurring significant hardware overhead. We use a bus based SoC simulation model to validate our test methodology. The test methodology involves addition of a test wrapper that can be configured for specific test needs. The methodology supports at-speed testing for delay faults and stuck-at testing of IP cores implementing full-scan.