On-chip SOC test platform design biased on IEEE 1500 standard

Authors:
Kuen-Jong Lee;Tong-Yu Hsieh;Ching-Yao Chang;Yu-Ting Hong;Wen-Cheng Huang
Affiliations:
Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan;Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan;Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan;Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan;Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2010

Citing 12
Cited 0

Testing Embedded-Core-Based System Chips

Computer
Embedded Software-Based Self-Test for Programmable Core-Based Designs

IEEE Design & Test
A Self-Test Methodology for IP Cores in Bus-Based Programmable SoCs

VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores

Proceedings of the conference on Design, automation and test in Europe - Volume 1
A High Speed BIST Architecture for DDR-SDRAM Testing

MTDT '05 Proceedings of the 2005 IEEE International Workshop on Memory Technology, Design, and Testing
InTeRail: A Test Architecture for Core-Based SOCs

IEEE Transactions on Computers
Test Efficiency Analysis and Improvement of SOC Test Platforms

ATS '07 Proceedings of the 16th Asian Test Symposium
Software-based self-testing with multiple-level abstractions for soft processor cores

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
STEAC: a platform for automatic SOC test integration

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Turbo1500: Core-Based Design for Test and Diagnosis

IEEE Design & Test
Broadcasting test patterns to multiple circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test Wrapper Design and Optimization Under Power Constraints for Embedded Cores With Multiple Clock Domains

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

IEEE 1500 Standard defines a standard test interface for embedded cores of a system-on-a-chip (SOC) to simplify the test problems. In this paper we present a systematic method to employ this standard in a SOC test platform so as to carry out on-chip at-speed testing for embedded SOC cores without using expensive external automatic test equipment. The cores that can be handled include scan-based logic cores, BIST-based memory cores, BIST-based mixed-signal devices, and hierarchical cores. All required test control signals for these cores can be generated on-chip by a single centralized test access mechanism (TAM) controller. These control signals along with test data formatted in a single buffer are transferred to the cores via a dedicated test bus, which facilitates parallel core testing. A number of design techniques, including on-chip comparison, direct memory access, hierarchical core test architecture, and hierarchical test bus design, are also employed to enhance the efficiency of the test platform. A sample SOC equipped with the test platform has been designed. Experimental results on both FPGA prototyping and real chip implementation confirm that the test platform can efficiently execute all test procedures and effectively identify potential defect(s) in the target circuit(s).