Fault tolerant and fault testable hardware design
Fault tolerant and fault testable hardware design
Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
Multiple error detection and identification via signature analysis
Journal of Electronic Testing: Theory and Applications
The Test Access Port and Boundary-Scan Architecture
The Test Access Port and Boundary-Scan Architecture
Fault-Secure Parity Prediction Arithmetic Operators
IEEE Design & Test
Synthesis of Multi-level Self-Checking Logic
Proceedings of the The IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Fault-secure shifter design: results and implementations
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A tool for automatic generation of self-checking data paths
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
Error-Control Techniques for Logic Processors
IEEE Transactions on Computers
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We describe a library of parameterized VHDLmodels for various concurrent fault detection circuits andmaintenance functions developed for simulation and synthesisof ASICs which support on-line testing and diagnostics insystems designed for high reliability and availability. Issuesassociated with the selection and modeling of the various on-linetesting functions are also discussed.