Logic testing and design for testability
Logic testing and design for testability
Fault-tolerant computing: theory and techniques; vol. 1
Fault-tolerant computing: theory and techniques; vol. 1
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
IEEE standard 1149.1-1990 on boundary scan: history, literature survey, and current status
Journal of Electronic Testing: Theory and Applications
An Effective BIST Scheme for ROM's
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Discrete Mathematics with Applications
Discrete Mathematics with Applications
The Test Access Port and Boundary-Scan Architecture
The Test Access Port and Boundary-Scan Architecture
A Universal Testability Strategy for Multi-Chip Modules Based on BIST and Boundary-Scan
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Built-In Self-Diagnostic Read-Only-Memories
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Test Strategies for a Family of Complex MCMs
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Error Control Coding, Second Edition
Error Control Coding, Second Edition
Fundamentals of MCM Testing and Design-for-Testability
Journal of Electronic Testing: Theory and Applications - Special issue on multi-chip testing and design for testability
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A system diagnosis technique for multichip module (MCM) ispresented. The proposed technique uses built-in probes for monitoringinternal responses and, with a signature analysis scheme based onerror correcting codes, identifies the probes where erroneous test responses have been detected. Conceptsfrom system diagnosis is used in conjunction withsignature analysis in developing the proposed MCM diagnosistechnique, where the resulting patterns of the faulty probes are usedin the identification of the faulty submodules (dies). The proposedtechnique offers a diagnostic capability in system functional test.