An introduction to the boundary scan standard: ANSI/IEEE Std 1149.1
Journal of Electronic Testing: Theory and Applications
The SPARC architecture manual: version 8
The SPARC architecture manual: version 8
The Test Access Port and Boundary-Scan Architecture
The Test Access Port and Boundary-Scan Architecture
A Case Study in the Use of Scan in microSparcTM Testing and Debug
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Design for Testability A Survey
IEEE Transactions on Computers
Silicon Debug: Scan Chains Alone Are Not Enough
ITC '99 Proceedings of the 1999 IEEE International Test Conference
System-on-Chip Test Architectures: Nanometer Design for Testability
System-on-Chip Test Architectures: Nanometer Design for Testability
| Hi-index | 0.00 |
microSPARC™ is a highly integrated, high volume, low-cast CMOS RISC microprocessor. To meet the design goals, it included fully synchronous logic with full testability support, using scannable flops and a JTAG-compliant clock controller. This paper describes the key features of the scan design and how they were used to maximize parallelism in system and tester environments, while reducing bottlenecks in functional and timing debug. The paper concludes with a discussion of lessons learned. A related paper [1] describes the methodologies used and benefits realized in the tester environment, along with data collected during the debug phase of the project.