The Test Access Port and Boundary-Scan Architecture
The Test Access Port and Boundary-Scan Architecture
Backplane Interconnect Test in a Boundary-Scan Environment
Proceedings of the IEEE International Test Conference on Test and Design Validity
A Proposed Method of Accessing 1149.1 in a Backplane Environment
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
| Hi-index | 0.00 |
ICs with IEEE 1149.1 Boundary Scan (BS) Architecture(a.k.a. JTAG) have been widely used in board level designto increase the testability. An end-to-end test methodologythat utilizes BS architecture for testing boards andsystems throughout the product life cycle is proposed. Theproposed test methodology includes a programmable dynamicBS test architecture and a series of test modulesthat take advantage of the test architecture for completefault coverage. Proposed design-for-testability (DFT)techniques guarantee the co-existence of BS testing withother system functions, such as in-system programming(ISP) and DSP JTAG emulation. At board level, programmabledynamic scan chains are used in a divide-andconquerfashion to increase the flexibility in the developmentphase (or design verification testing (DVT)). Besides,since the DFT techniques are programmable, theycan be used as design-for-diagnosis (DFD) to increase diagnosis resolution during DVT. Address Scan Port (ASP)chips are used to enable multi-drop test bus architecturefor backplane testing as well as system embedded testing.Other advanced techniques, such as analog subsystemtesting and board-level built-in self-test, as well ashow to re-use BS architecture in in-circuit testing (ICT)and manufacture testing are also parts of the proposedmethodology that takes advantage of BS architecture toprovide full scale testing for systems.