Fault tolerance in co-evolutionary communication of EHW modules
Computers & Mathematics with Applications
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Genetic learning based fault tolerant models for digital systems
Applied Soft Computing
Using negative correlation to evolve fault-tolerant circuits
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
A genetic representation for evolutionary fault recovery in Virtex FPGAs
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
POEtic tissue: an integrated architecture for bio-inspired hardware
ICES'03 Proceedings of the 5th international conference on Evolvable systems: from biology to hardware
Robustness of evolvable hardware in the case of fault and environmental change
ROBIO'09 Proceedings of the 2009 international conference on Robotics and biomimetics
The route to a defect tolerant LUT through artificial evolution
Genetic Programming and Evolvable Machines
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This paper considers the ability of an evolved circuit to acquire fault tolerance by including fault conditions within the fitness measure of the evolutionary process. A simple oscillator circuit, implemented on a Xilinx FPGA, showed a 12 fold increase in fault-tolerance when compared to a control oscillator using realistic faults.