Comparing models of computation
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
Software performance estimation strategies in a system-level design tool
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Models of computation for embedded system design
System-level synthesis
A universal communication model for an automotive system integration platform
Proceedings of the conference on Design, automation and test in Europe
Reliable estimation of execution time of embedded software
Proceedings of the conference on Design, automation and test in Europe
Embedded UML: a merger of real-time UML and co-design
Proceedings of the ninth international symposium on Hardware/software codesign
Synchronous Programming of Reactive Systems
Synchronous Programming of Reactive Systems
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Modern automotive applications such as Drive-by-Wire are implemented over distributed architectures where electronic control units (ECU's) communicate via broadcast buses. In this paper, we present the concept of virtual integration platform for automotive applications. The platform provides the basis for early analysis and validation of distributed applications, therefore enhancing the current model based development process techniques that are applied to one ECU at a time. The virtual prototype includes both functional and performance (time) models of the application software, scheduling policies, and the bus communication protocols. As a result, since design errors can be found earlier in the design process before the different sub-systems are integrated in the car, savings in both production and development costs can be achieved. The virtual integration platform concept is supported by an integrated IP-based tool environment for authoring, integration, and validation. First, a model of the distributed application is built by composing models of HW and SW components. The models can be either authored or imported from different tools. Functional simulation of the overall distributed control algorithm can be carried out first. Then, the mapping phase can take place: subfunctions of the control algorithm are mapped to architectural resources (CPUs), and zero-time communication links between the sub-functions are mapped to bus protocol delay models. Changing mappings, parameters such as task priorities, and bus schedule enables the exploration of alternative implementations. The validation is carried out by simulating the resulted virtual prototype of the distributed control algorithm running on the ECU network. The design environment shortens design turn-around time by supporting (semi)-automatic configuration of the architecture model (e.g. frame packaging, redundancy level, communication matrix, bus and RTOS scheduling, etc.).