Communications of the ACM
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Dynamo: a transparent dynamic optimization system
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Readings in hardware/software co-design
Readings in hardware/software co-design
Binary Translation: Static, Dynamic, Retargetable?
ICSM '96 Proceedings of the 1996 International Conference on Software Maintenance
Xen and the art of virtualization
SOSP '03 Proceedings of the nineteenth ACM symposium on Operating systems principles
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Programming models and HW-SW interfaces abstraction for multi-processor SoC
Proceedings of the 43rd annual Design Automation Conference
Standards: The P1685 IP-XACT IP Metadata Standard
IEEE Design & Test
EDA for IC System Design, Verification, and Testing (Electronic Design Automation for Integrated Circuits Handbook)
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
QEMU, a fast and portable dynamic translator
ATEC '05 Proceedings of the annual conference on USENIX Annual Technical Conference
IEEE Computer Architecture Letters
Platform-based software design flow for heterogeneous MPSoC
ACM Transactions on Embedded Computing Systems (TECS)
Efficient implementation of native software simulation for MPSoC
Proceedings of the conference on Design, automation and test in Europe
FEMU: a firmware-based emulation framework for SoC verification
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Practical design space exploration of an h264 decoder for handheld devices using a virtual platform
PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Fast simulation of systems embedding VLIW processors
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper, we investigate the use of instruction set simulators (ISS) based on binary translation to accelerate full timed multiprocessor system simulation at transaction level. To have an accurate timing behavior, we had to firstly solve timing issues in processor modeling, secondly define fast and precise cache models, and thirdly solve the synchronization issues due to the different models of computation used in the ISSes and in the rest of the system. We present an integration solution that covers these issues and detail its implementation. We have experimented our proposal using processors models provided by the QEMU framework to replace the existing ISSes and SystemC TLM as simulation environment for the whole platform. This approach proposes a range of solutions trading off simulation speed versus accuracy. The experiments show that even for the most precise configuration, the simulation speedup is still significant.