Efficiently computing static single assignment form and the control dependence graph
ACM Transactions on Programming Languages and Systems (TOPLAS)
DAISY: dynamic compilation for 100% architectural compatibility
Proceedings of the 24th annual international symposium on Computer architecture
Dynamo: a transparent dynamic optimization system
PLDI '00 Proceedings of the ACM SIGPLAN 2000 conference on Programming language design and implementation
Machine-adaptable dynamic binary translation
DYNAMO '00 Proceedings of the ACM SIGPLAN workshop on Dynamic and adaptive compilation and optimization
A universal technique for fast and flexible instruction-set architecture simulation
Proceedings of the 39th annual Design Automation Conference
Binary Translation: Static, Dynamic, Retargetable?
ICSM '96 Proceedings of the 1996 International Conference on Software Maintenance
Proceedings of the international symposium on Code generation and optimization: feedback-directed and runtime optimization
Efficient implementation of the smalltalk-80 system
POPL '84 Proceedings of the 11th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Optimizing Dynamic Binary Translation for SIMD Instructions
Proceedings of the International Symposium on Code Generation and Optimization
QEMU, a fast and portable dynamic translator
ATEC '05 Proceedings of the annual conference on USENIX Annual Technical Conference
High Speed CPU Simulation Using LTU Dynamic Binary Translation
HiPEAC '09 Proceedings of the 4th International Conference on High Performance Embedded Architectures and Compilers
Using binary translation in event driven simulation for fast and flexible MPSoC simulation
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
An Optimization Approach for QEMU
ICISE '09 Proceedings of the 2009 First IEEE International Conference on Information Science and Engineering
On MPSoC Software Execution at the Transaction Level
IEEE Design & Test
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Virtual prototyping of MPSoCs requires fast processor simulation models. Dynamic binary translation is an efficient technology for instruction set simulation, but as it is basically used for effortless code migration, it targets mostly general purpose processors. As many heterogeneous MPSoCs include VLIW processors, we propose and detail in this paper a strategy to perform dynamic binary translation of VLIW codes on scalar architectures for simulation purposes. Our simulation experiments show that it is a few orders of magnitude faster than direct instruction interpretation, although the translator includes no optimization.