A critical-section-level timing synchronization approach for deterministic multi-core instruction set simulations

  • Authors:

  • Fan-Wei Yu;Bo-Han Zeng;Yu-Hung Huang;Hsin-I Wu;Che-Rung Lee;Ren-Song Tsay

  • Affiliations:

  • National Tsing Hua University, Hsinchu, Taiwan;National Tsing Hua University, Hsinchu, Taiwan;National Tsing Hua University, Hsinchu, Taiwan;National Tsing Hua University, Hsinchu, Taiwan;National Tsing Hua University, Hsinchu, Taiwan;National Tsing Hua University, Hsinchu, Taiwan

  • Venue:
  • Proceedings of the Conference on Design, Automation and Test in Europe
  • Year:
  • 2013

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Abstract

This paper proposes a Critical-Section-Level timing synchronization approach for deterministic Multi-Core Instruction-Set Simulation (MCISS). By synchronizing at each lock access instead of every shared-variable access and using a simple lock usage status managing scheme, our approach significantly improves simulation performance while executing all critical sections in a deterministic order. Experiments show that our approach performs 295% faster than the shared-variable synchronization approach on average and can effectively facilitate system-level software/hardware co-simulation.