Performance modeling of parallel applications on MPSoCs

  • Authors:

  • Marco Lattuada;Christian Pilato;Antonino Tumeo;Fabrizio Ferrandi

  • Affiliations:

  • Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy;Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy;Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy;Dipartimento di Elettronica e Informazione, Politecnico di Milano, Milano, Italy

  • Venue:
  • SOC'09 Proceedings of the 11th international conference on System-on-chip
  • Year:
  • 2009

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Abstract

In this paper we present a new technique for automatically measuring the performance of tasks, functions or arbitrary parts of a program on a multiprocessor embedded system. The technique instruments the tasks described by OpenMP, used to represent the task parallelism, while ad hoc pragmas in the source indicate other pieces of code to profile. The annotations and the instrumentation are completely target-independent, so the same code can be measured on different target architectures, on simulators or on prototypes. We validate the approach on a single and on a dual LEON 3 platform synthesized on FPGA, demonstrating a low instrumentation overhead. We show how the information obtained with this technique can be easily exploited in a Hardware/Software design space exploration tool, by estimating, with good accuracy, the speed-up of a parallel application given the profiling on the single processor prototype.