Low-power and High-Speed V VLSI Design with Low Supply Voltage through Cooperation between Levels

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ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
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2002

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Post-layout leakage power minimization based on distributed sleep transistor insertion

Proceedings of the 2004 international symposium on Low power electronics and design

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Abstract

In this paper, methods to achieve low-power and high-speed VLSI's are described with the emphasis on cooperation between levels. To suppress the leakage current in a standby mode, Boosted Gate MOS (BGMOS) is effective, which is based on cooperation between technology level and circuit level. To reduce the power in an active mode, VDD-hopping and VTH-hopping are promising, which are cooperative approaches between circuit and software. Power consumed in interconnect system is another issue in low-voltage deep-submicron designs. A cooperative approach between VLSI and assembly to the interconnect power problem is also discussed.