Understanding and minimizing ground bounce during mode transition of power gating structures
Proceedings of the 2003 international symposium on Low power electronics and design
Post-layout leakage power minimization based on distributed sleep transistor insertion
Proceedings of the 2004 international symposium on Low power electronics and design
Design and optimization of multithreshold CMOS (MTCMOS) circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A programmable resistive power grid for post-fabrication flexibility and energy tradeoffs
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
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Heterogeneous systems-on-chip pose a challenge for power delivery given the variety of needs for different components. In this paper, we describe recent work that leverages power switches and conventional EDA toolflows to implement a set of power delivery schemes that provide a flexible, adaptable range of options for power management of SoCs for which energy efficiency is important. We first present an enhanced dynamic voltage scaling (DVS) scheme that uses power switches to provide rapid changes in the energy-speed operating point to match workloads at a component level. To demonstrate this approach, we describe a data flow processor chip in 90nm CMOS that supports flexible operation from 0.25V with super high energy efficiency up to GHz speeds at 1.2V. This chip shows that our low overhead method to scale energy consumption with the performance requirement supports both high performance and ultra low energy (10X reduction in energy per operation) in the same circuit. We discuss power switch design for this scheme and investigate strategies for optimizing power switches for different operating modes. Finally, we show how segmented power switches offer several advantages for flexibly managing leakage and for modulating local voltages with low overhead.