Precomputation-based sequential logic optimization for low power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Guarded evaluation: pushing power management to logic synthesis/design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Dynamic Power Management: Design Techniques and CAD Tools
Dynamic Power Management: Design Techniques and CAD Tools
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In this paper, a power management technique based on dynamic frequency scaling is proposed. The proposed technique targets digital receivers employing adaptive sampling. Such circuits over-sample the analogue input signal, in order to succeed timing synchronization. The proposed technique introduces power savings by forcing the receiver to operate only on the "correct" data for the time intervals during which synchronization is achieved. The simple architectural modifications, needed for the application of the proposed strategy, are described. As test-vehicle a number of FIR filters, which are the basic components of almost every digital receiver, are used. The experimental results prove that the application of the proposed technique introduces significant power savings, while negligibly increasing area and critical path.