Precomputation-based sequential logic optimization for low power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
CDMA: principles of spread spectrum communication
CDMA: principles of spread spectrum communication
Practical low power digital VLSI design
Practical low power digital VLSI design
Low-power CMOS wireless communications: a wideband CDMA system design
Low-power CMOS wireless communications: a wideband CDMA system design
Low Power Digital CMOS Design
Principles of Digital Communication and Coding
Principles of Digital Communication and Coding
Low-Power Digital VLSI Design Circuits and Systems
Low-Power Digital VLSI Design Circuits and Systems
VLSI implementation of rake receiver for IS-95 CDMA Testbed using FPGA
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
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In this paper, we address the issues of designing lowpower VLSI implementation of the Code DivisionMultiple Access (CDMA) receiver. Among all the digitalfunctional blocks of a CDMA receiver, the RAKEreceiver and the Viterbi decoder are the mostcomputational intensive and hence consume most of thepower. In this work, we propose new VLSI architecturesfor these two functional blocks which consumesignificantly lower power. In particular, were-organize the structure of the pilot-aided RAKEdemodulator to reduce the operational frequency of thearithmetic components and we propose a newAdd-Compare-Select (ACS) architecture for the Viterbidecoder which can reduce the complexity of thecomputation. Also a novel pre-computationalarchitecture is proposed to further reduce the powerconsumption of the ACS unit. Experimental results showsignificant reduction in power consumption.