Implementation of hardware-accelerated scalable parallel random number generators

Authors:
JunKyu Lee;Gregory D. Peterson;Robert J. Harrison;Robert J. Hinde
Affiliations:
Department of Electrical Engineering and Computer Science, University of Tennessee, Knoxville, TN;Department of Electrical Engineering and Computer Science, University of Tennessee, Knoxville, TN;Department of Chemistry, University of Tennessee, Knoxville, TN;Department of Chemistry, University of Tennessee, Knoxville, TN
Venue:
VLSI Design - Special issue on selected papers from the midwest symposium on circuits and systems
Year:
2010

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Abstract

The Scalable Parallel Random Number Generators (SPRNGs) library is widely used in computational science applications such as Monte Carlo simulations since SPRNG supports fast, parallel, and scalable random number generation with good statistical properties. In order to accelerate SPRNG, we develop a Hardware-Accelerated version of SPRNG (HASPRNG) on the Xilinx XC2VP50 Field Programmable Gate Arrays (FPGAs) in the Cray XD1 that produces identical results. HASPRNG includes the reconfigurable logic for FPGAs along with a programming interface which performs integer random number generation. To demonstrate HASPRNG for Reconfigurable Computing (RC) applications, we also develop a Monte Carlo π-estimator for the Cray XD1. The RC Monte Carlo π-estimator shows a 19.1× speedup over the 2.2 GHz AMD Opteron processor in the Cray XD1. In this paper we describe the FPGA implementation for HASPRNG and a π-estimator example application exploiting the fine-grained parallelism and mathematical properties of the SPRNG algorithm.