Performance effects of pipeline architecture on an FPGA-based binary32 floating point multiplier

Authors:
Xianyang Jiang;Peng Xiao;Meikang Qiu;Gaofeng Wang
Affiliations:
Institute of Microelectronics and Information Technology, Wuhan University, Wuhan, China;Institute of Microelectronics and Information Technology, Wuhan University, Wuhan, China;ECE Department, University of Kentucky, USA;Institute of Microelectronics and Information Technology, Wuhan University, Wuhan, China
Venue:
Microprocessors & Microsystems
Year:
2013

Citing 7
Cited 0

FPGAs vs. CPUs: trends in peak floating-point performance

FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Low-Power Multiple-Precision Iterative Floating-Point Multiplier with SIMD Support

IEEE Transactions on Computers
Design of Generic Floating Point Multiplier and Adder/Subtractor Units

UKSIM '10 Proceedings of the 2010 12th International Conference on Computer Modelling and Simulation
Variable-latency floating-point multipliers for low-power applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bridge floating-point fused multiply-add design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Clock-less Design for Reconfigurable Floating Point Multiplier

CIMSIM '11 Proceedings of the 2011 Third International Conference on Computational Intelligence, Modelling & Simulation
Configurable Multimode Embedded Floating-Point Units for FPGAs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

High pipeline depth architecture with pipeline stage more than five is rarely adopted in existing multipliers for real world applications. In this paper, a field programmable gate array (FPGA) based binary32 floating point multiplier (FPM) is presented to support variety of pipeline depth and the effects of pipeline architecture have been investigated. Pipeline architecture is formulated based on radix-4 Booth recoding approach, an improved Wallace tree, and partial product accumulation. Upon detail and quantitative investigation on the proposed architecture on both cutting edge Xilinx and Altera devices, pipeline depth affects maximum running frequency much more than power consumption, and the pipeline depth should be limited to obtain maximum running frequency for binary32 FPM on both cutting edge target devices, which is consistent to the previous study. Meanwhile, the study demonstrates the pipeline depth to reach at peak performance is lower than that of targeting at FPGA device with 4-input LUTs years ago.