System identification: theory for the user
System identification: theory for the user
Discrete-time control systems (2nd ed.)
Discrete-time control systems (2nd ed.)
Digital Controller Implementation and Fragility: A Modern Perspective
Digital Controller Implementation and Fragility: A Modern Perspective
Computer Controlled Systems: Theory and Design
Computer Controlled Systems: Theory and Design
FPGAs vs. CPUs: trends in peak floating-point performance
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Convex Optimization
C Based Hardware Design for Wireless Applications
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Design automation for streaming systems
Design automation for streaming systems
High-Performance Reduction Circuits Using Deeply Pipelined Operators on FPGAs
IEEE Transactions on Parallel and Distributed Systems
Journal of Parallel and Distributed Computing
Matrix Computations on Heterogeneous Reconfigurable Systems
FCCM '08 Proceedings of the 2008 16th International Symposium on Field-Programmable Custom Computing Machines
A view of the parallel computing landscape
Communications of the ACM - A View of Parallel Computing
Proceedings of the 24th ACM International Conference on Supercomputing
BLAS Comparison on FPGA, CPU and GPU
ISVLSI '10 Proceedings of the 2010 IEEE Annual Symposium on VLSI
High-performance floating-point implementation using FPGAs
MILCOM'09 Proceedings of the 28th IEEE conference on Military communications
CIT '10 Proceedings of the 2010 10th IEEE International Conference on Computer and Information Technology
Automatic generation of fpga-specific pipelined accelerators
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
A novel processor architecture for real-time control
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
IEEE Transactions on Signal Processing - Part II
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The parallelism attained by the use of Field Programmable Gate Arrays (FPGAs) has shown remarkable potential for accelerating control systems applications. This comes at a time when well established methods based on inherited serial Central Processor Units (CPUs) cannot guarantee solutions for the increasing execution speed demands. However, the transition from serial to parallel architectures represents a tremendous challenge due to overwhelming numbers of unexplored options and conflicting factors. The work presented achieves a parallelisation characterisation for generic MIMO systems using stand-alone FPGA implementations. The main contribution is that a very fine subset of possible serial/parallel implementations is obtained. This is used to achieve a flexible trade-off between cost and performance. Automatic optimisation of latency, occupied FPGA area and execution speed is attained and justified in respect to most of the feasible scenarios.