A novel processor architecture for real-time control

Authors:
Xiaofeng Wu;Vassilios Chouliaras;Jose Nunez-Yanez;Roger Goodall;Tanya Vladimirova
Affiliations:
Surrey Space Center, Department of Electronic Engineering, University of Surrey, Guildford, UK;Department of Electronic and Electrical Engineering, Loughborough University, Leicestershire, UK;Department of Electronic Engineering, University of Bristol, Bristol, UK;Department of Electronic and Electrical Engineering, Loughborough University, Leicestershire, UK;Surrey Space Center, Department of Electronic Engineering, University of Surrey, Guildford, UK
Venue:
ACSAC'06 Proceedings of the 11th Asia-Pacific conference on Advances in Computer Systems Architecture
Year:
2006

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Automatic parallelisation for LTI MIMO state space systems using FPGAs. An optimisation for cost & performance

Journal of Parallel and Distributed Computing

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Abstract

This paper describes a control system processor architecture based on ΔΣ modulation (ΔΣ-CSP). The ΔΣ-CSP uses 1-bit processing which is a new concept in digital control to remove multi-bit multiplications. A simple conditional-negate-and-add (CNA) unit is proposed for most operations of control laws. For this reason, the targeted processor is small and very fast, making it ideal for embedded real-time control applications. The ΔΣ-CSP has been implemented as a VLSI hard macro in a high-performance 0.13μm silicon process. Results show that it compares very favorably to other digital processors in terms of area and clock frequency.