Reconfigurable custom floating-point instructions (abstract only)
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Reducing the cost of floating-point mantissa alignment and normalization in FPGAs
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
FPGA-specific synthesis of loop-nests with pipelined computational cores
Microprocessors & Microsystems
Faithful single-precision floating-point tangent for FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Self-Alignment Schemes for the Implementation of Addition-Related Floating-Point Operators
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Optimizing floating point units in hybrid FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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- This paper will describe the architecture of a compiler which will convert an untimed C description of a floating point expression into a synthesizable datapath optimized for FPGAs. The concept of floating point fused datapath synthesis will be reviewed, along with the expected functional efficiency gains. The dataflow graph structure used by the compiler will be detailed, followed by the description of the restructuring and optimizations, as well as the required data integrity considerations. In particular, datapath architecture considerations for improved FPGA fitting will be explored. Application examples for a matrix calculations will be used to illustrate the improvements of the compiled datapath compared to the traditional core based approach, and the mechanisms behind them.