Reduction of latency and resource usage in bit-level pipelined data paths for FPGAs

• Authors:

• P. Kollig;B. M. Al-Hashimi

• Affiliations:

• School of Engineering and Advanced Technology, Staffordshire University, Beaconside, Stafford ST18 OAD, U.K.;School of Engineering and Advanced Technology, Staffordshire University, Beaconside, Stafford ST18 OAD, U.K.

• Venue:
• FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
• Year:
• 1999