On-the-fly conversion of redundant into conventional representations
IEEE Transactions on Computers
Performance of iterative computation in self-timed rings
Journal of VLSI Signal Processing Systems - Special issue: asynchronous circuit design for VLSI signal processing
Synthesis of hazard-free control circuits from asynchronous finite state machines specifications
Journal of VLSI Signal Processing Systems - Special issue: asynchronous circuit design for VLSI signal processing
Algorithms for Synthesis and Testing of Asynchronous Circuits
Algorithms for Synthesis and Testing of Asynchronous Circuits
A Self-Timed Divider Using RSD Number System
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
Design of a GaAs redundant divider
VLSI '93 Proceedings of the IFIP TC10/WG 10.5 International Conference on Very Large Scale Integration
The Correspondence Between Methods of Digital Division and Multiplier Recoding Procedures
IEEE Transactions on Computers
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This paper describes a self-timed integrated circuit for division and square-root extraction. First it concentrates on the development and the proof of a new mathematical algorithm. Then the design methodology and the architecture of a self-timed circuit implementing a simplified version of the algorithm is presented. The algorithm relies on two functional blocks, each simple enough to be fully detailed at the logic level in this paper. Besides its simplicity, the novelty of the algorithm lies in the fact that it delivers the quotient or the square root in conventional binary notation. The final remainder only has to be eventually converted.