A reversible carry-look-ahead adder using control gates
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Optimized reversible binary-coded decimal adders
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CSR'07 Proceedings of the Second international conference on Computer Science: theory and applications
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The design of fast arithmetic logic circuits is an important research topic for reversible and quantum computing. A special challenge in this setting is the computation of standard arithmetical functions without the generation of garbage. The CDKM-adder is a recent garbage-less reversible (quantum) ripple-carry adder. We optimize this design with a novel parallelization scheme wherein mparallel k-bit CDKM-adders are combined to form a reversible mk-bit ripple-block carry adderwith logic depth $\mathcal{O}(m+k)$ for a minimallogic depth $\mathcal{O}(\sqrt{mk})$, thus improving on the mk-bit CDKM-adder logic depth $\mathcal{O}(m\cdot k)$. We also show designs for garbage-less reversible set-less-than circuits. We compare the circuit costs of the CDKM and parallel adder in measures of circuit delay, width, gate and transistor count, and find that the parallelized adder offers significant speedups at realistic word sizes with modest parallelization overhead.