Quantum ternary parallel adder/subtractor with partially-look-ahead carry

Authors:
Mozammel H. A. Khan;Marek A. Perkowski
Affiliations:
Department of Computer Science and Engineering, East West University, 43 Mohakhali, Dhaka 1212, Bangladesh;Department of Electrical and Computer Engineering, Portland State University, Portland, OR 97207-0751, USA
Venue:
Journal of Systems Architecture: the EUROMICRO Journal
Year:
2007

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Abstract

Multiple-valued quantum circuits are a promising choice for future quantum computing technology since they have several advantages over binary quantum circuits. Binary parallel adder/subtractor is central to the ALU of a classical computer and its quantum counterpart is used in oracles - the most important part that is designed for quantum algorithms. Many NP-hard problems can be solved more efficiently in quantum using Grover algorithm and its modifications when an appropriate oracle is constructed. There is therefore a need to design standard logic blocks to be used in oracles - this is similar to designing standard building blocks for classical computers. In this paper, we propose quantum realization of a ternary full-adder using macro-level ternary Feynman and Toffoli gates built on the top of ion-trap realizable ternary 1-qutrit and Muthukrishnan-Stroud gates. Our realization has several advantages over the previously reported realization. Based on this realization of ternary full-adder we propose realization of a ternary parallel adder with partially-look-ahead carry. We also show the method of using the same circuit as a ternary parallel adder/subtractor.