A minimum test set for multiple fault detection on ripple carry adders
IEEE Transactions on Computers
Testing in two-dimensional iterative logic arrays
Computers and Mathematics with Applications - Diagnosis and reliable design of VLSI systems
The Design of a Testable Parallel Multiplier
IEEE Transactions on Computers
Easily Testable Iterative Logic Arrays
IEEE Transactions on Computers
DETECTION OF MULTIPLE FAULTS IN TWO-DIMENSIONAL ILAs
DETECTION OF MULTIPLE FAULTS IN TWO-DIMENSIONAL ILAs
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We provide test sets proportional to the sum of the two dimensions of the array for a large class of cells, which allow us to test rows (or columns) of cells of the array independently. Constant length test sets for array multipliers have been found under the single faulty cell model if the array is modified, and otherwise test sets are proportional to the number of cells. We can verify the full adder array of a combinational n脳m multiplier in O(n + m) tests under the Multiple Faulty Cell (MFC) model. The entire multiplier, including the AND gates which generate the summands, can be verified after applying the same modifications which make the multiplier C-testable under the single faulty cell model.