Easily Testable Iterative Logic Arrays
IEEE Transactions on Computers
Constant testability of combinational cellular tree structures
Journal of Electronic Testing: Theory and Applications
Design and testing of regular circuits (VLSI)
Design and testing of regular circuits (VLSI)
Testability of Convergent Tree Circuits
IEEE Transactions on Computers
Properties of the input pattern fault model
ICCD '97 Proceedings of the 1997 International Conference on Computer Design (ICCD '97)
Testing and error detection in iterative logic arrays
Testing and error detection in iterative logic arrays
Easily Testable Cellular Carry Lookahead Adders
Journal of Electronic Testing: Theory and Applications
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The testability of a class of regular circuits calleddivergent trees is investigated under a functional fault model. Divergent trees include such practical circuits as decoders anddemultiplexers. We prove that uncontrolled divergent trees aretestable with a fixed number of test patterns (C-testable) if andonly if the module function is surjective. Testable controlled treesare also surjective but require sensitizing vectors for errorpropagation. We derive the conditions for testing controlleddivergent trees with a test set whose size is proportional to thenumber of levels p found in the tree (L-testability). By viewing a tree as overlapping arrays of various types, we also deriveconditions for a controlled divergent tree to be C-testable. Typicaldecoders/demultiplexers are shown to only partially satisfy L- andC-testability conditions but a design modification that ensuresL-testability is demonstrated.