An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs
Journal of Electronic Testing: Theory and Applications
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Self-Measurement of Combinatorial Circuit Delays in FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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The objective of this paper is to improve delay fault testing of SRAM-BasedFPGAs. We have analyzed the physical behavior of resistive opens in a Look-Up Table(LUT) in previous papers and we have shown that i) these ones can change the propagationdelay of the LUT and ii) the delay due to them varies depending on their size and theirlocation. In this paper, we first show that resistive shorts are susceptible to make delay faultson the LUT output, leading to the same conclusions. As a result, we next show that the two-pattern pair and the implemented function of the LUT can significantly modify thesensitization of these defects, until making them non-observable on output. As a consequence,the basic properties for generating test vectors are not sufficient and new conditions arerequired to guarantee a most efficient delay test in a Manufactured-Oriented Test (MOT)context and in an Application-Oriented Test (AOT) context as well.