Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices

Authors:
Kazuya Katsuki;Manabu Kotani;Kazutoshi Kobayashi;Hidetoshi Onodera
Affiliations:
Kyoto University, Kyoto, Japan;Kyoto University, Kyoto, Japan;Kyoto University, Kyoto, Japan;Kyoto University, Kyoto, Japan
Venue:
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Year:
2006

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ACM Transactions on Reconfigurable Technology and Systems (TRETS)

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Abstract

It is possible to enhance speed and yield of reconfigurable devices utilizing WID variations. An LUT array LSI is fabricated on a 90nm process to measure WID and D2D variations. Performance fluctuations are measured by counting the number of LUTs through which a signal is passing within a certain time. D2D and WID variations are clearly observed by the measurement.