Proceedings of the 37th Annual Design Automation Conference
Model and analysis for combined package and on-chip power grid simulation
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Design of High-Performance Microprocessor Circuits
Design of High-Performance Microprocessor Circuits
Random walks in a supply network
Proceedings of the 40th annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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A circuit block model and methodology for accurate power supply noise analysis, taking the impact of power supply noise on the current consumption into account, is presented. This enables high transient accuracy even at excessive power supply noise. Further improvement is obtained by an adaptive model for the capacitance of switching gates. Simulations for various power grids and test circuits are compared between a state of the art and the improved modelling. Simulation error of power supply noise was reduced by 4.7X - 20X at a simulation run time penalty of roughly 20%. This makes it especlally helpful for low power SoC designs, with high transient IR-Drop and multi-frequency domains, where transient accuracy is of concern.