Model order-reduction of RC(L) interconnect including variational analysis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A Modification of Davidon's Minimization Method to Accept Difference Approximations of Derivatives
Journal of the ACM (JACM)
Impact of interconnect variations on the clock skew of a gigahertz microprocessor
Proceedings of the 37th Annual Design Automation Conference
Impact of Interconnect Process Variations on Memory Performance and Design
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Statistical static timing analysis: A survey
Integration, the VLSI Journal
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The complicated manufacturing processes dictate that process variations are unavoidable in today's VLSI products. Unlike device variations, which can be captured by worst/best case corner points, the effects of interconnect variations are context-dependent, which makes it difficult to capture the true worst-case timing performance. This paper discusses an efficient method to explore the extreme values of performance metrics and the specific parameters that will create these extreme performances. The described approach is based on a iterative search technique which facilitates its proper search direction by calculating an explicit analytical approximation model.