Post-bond stack testing for 3d stacked IC

Authors:
Surajit Kumar Roy;Dona Roy;Chandan Giri;Hafizur Rahaman
Affiliations:
Department of Information Technology, Bengal Engineering and Science University, India;Department of Information Technology, Bengal Engineering and Science University, India;Department of Information Technology, Bengal Engineering and Science University, India;Department of Information Technology, Bengal Engineering and Science University, India
Venue:
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
Year:
2012

Citing 3
Cited 0

Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip

Journal of Electronic Testing: Theory and Applications
Test Challenges for 3D Integrated Circuits

IEEE Design & Test
Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

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Abstract

In the embedded system design Through-silicon-via (TSV) based 3D stacked ICs (SICs) play an important role in semiconductor industry. But testing of these SICs are required during 3D assembly because different die stacking steps may introduce defects. In this paper, we address test architecture optimization for 3D stacked ICs implemented with hard die means where die-level test architecture is fixed. We consider two different SIC configurations and derive optimal solution to minimize overall test time when complete stack and multiple partial stacks, need to be tested. Results are performed for two handcrafted 3D SICs comprising of various SoCs from ITC'02 SoC test benchmarks. In this work we consider the test architecture optimization for 3D SIC where each die consists of one SoC. We present test schedules and corresponding test lengths for every multiple insertions and also show that total test lengths are decreased with the increasing number of test pins.