A Hardware and Software Monitor for High-Level System-on-Chip Verification
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Reusing an on-chip network for the test of core-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Power efficiency for variation-tolerant multicore processors
Proceedings of the 2006 international symposium on Low power electronics and design
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
HW-SW emulation framework for temperature-aware design in MPSoCs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Task activity vectors: a new metric for temperature-aware scheduling
Proceedings of the 3rd ACM SIGOPS/EuroSys European Conference on Computer Systems 2008
Full-system chip multiprocessor power evaluations using FPGA-based emulation
Proceedings of the 13th international symposium on Low power electronics and design
Dynamic Power and Thermal Management of NoC-Based Heterogeneous MPSoCs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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The use of efficient and dynamic power dissipation management mechanisms is crucial in upcoming, complex and dynamic multi-core Systems-on-Chip. In such systems, static approaches are inadequate to capture the dynamic system behavior, while at the same time, their complexity makes the use of extensive, accurate simulation-based power estimation computationally difficult or prohibitive. This paper proposes dynamically programmable hardware monitors with insignificant cost in silicon area, easily integrated with multi-core Systems-on-Chip, which act non-intrusively in support of real-time identification of tasks' behavior and adaptive management of varying workload. We extract instruction and data activity metrics in order to estimate applications power phase in less than 10 clock cycles. Using "binary" on/off accelerators in conjuction with a distributed algorithm for workload throttling fast and efficient power throttling is achieved proportional to tasks power profile.