SAT-based generation of compressed skewed-load tests for transition delay faults
Microprocessors & Microsystems
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Simulation data are presented for eleven benchmark circuits to show how test pattern correlation in a scan-path design circuit adversely affects delay fault coverage, and to demonstrate that most undetected delay faults caused by correlation of test patterns are close to the outputs of latches. Topology-based latch correlation measures are introduced and used by a companion latch arrangement algorithm to guide the placement of latches in a scan-path design, with the objective of minimizing the effect of correlation and maximizing the coverage of delay faults. Simulation results with benchmark circuits indicate that the scan-path found by the algorithm clearly achieves better delay fault coverage than a scan-path having no deliberate arrangement. The data also indicates that the algorithm is most effective in covering delay faults that are located nearest the latch outputs of the circuit. The approach has an advantage over other arrangement schemes in that it is simple to implement and does not require significant computational time even for large circuits