Reusing Learned Information in SAT-based ATPG

Authors:
Gorschwin Fey;Tim Warode;Rolf Drechsler
Affiliations:
University of Bremen, 28359 Bremen, Germany;University of Bremen, 28359 Bremen, Germany;University of Bremen, 28359 Bremen, Germany
Venue:
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Year:
2007

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Abstract

The robustness of engines for ATPG has to be improved to cope with the growing size of circuits. Recently, SAT-based ATPG approaches have been shown to be very robust even on large industrial circuits. Here, we propose techniques to further improve the efficiency by embedding learning techniques in a SATbased ATPG engine. We provide a heuristic to apply incremental SAT when enumerating faults and a technique to apply circuit-based learning where incremental SAT is not applicable. The correctness of circuit-based learning is proven. Experimental results on large benchmarks show the efficiency.