MONSOON: SAT-Based ATPG for Path Delay Faults Using Multiple-Valued Logics
Journal of Electronic Testing: Theory and Applications
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In this paper, we propose a new approach to efficiently identify paths for delay testing. We use a realistic delay model and several new concepts (timing threshold, settling times [14], and timing blocking line) and algorithms, to identify a set of paths that is guaranteed to include all paths that may potentially cause a timing error if the accumulated values of additional delays along circuit paths is upper bounded by a desired limit, ... The first phase of the proposed approach identifies a small subset of all possible paths in the circuit for further analysis. Since this phase only requires breadth-first static timing analysis (forward and backward), its complexity is independent of the number of paths in the circuit as well as the number of all possible two-vector sequences that may be applied to the circuit. We then use new conditions for functional sensitization that help identify paths that may be functionally sensitizable and have the potential of causing timing errors if accumulated values of additional delays along any path is upper bounded by ... The results show that without any search, the proposed approach identifies a near minimal number of paths at low complexity.