A Fault-Tolerant Modular Architecture for Binary Trees
IEEE Transactions on Computers - The MIT Press scientific computation series
Reconfigurable Tree Architectures Using Subtree Oriented Fault Tolerance
IEEE Transactions on Computers
Embedding graphs in books: a layout problem with applications to VLSI design
SIAM Journal on Algebraic and Discrete Methods
Vertex types in book-embeddings
SIAM Journal on Discrete Mathematics
Computational Aspects of VLSI
Design and Analysis of a Generalized Architecture for Reconfigurable m-ary Tree Structures
IEEE Transactions on Computers
A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors
IEEE Transactions on Computers
Embryonics: A Bio-Inspired Cellular Architecture with Fault-Tolerant Properties
Genetic Programming and Evolvable Machines
IEEE Transactions on Computers
Routing in Modular Fault-Tolerant Multiprocessor Systems
IEEE Transactions on Parallel and Distributed Systems
FTCS '96 Proceedings of the The Twenty-Sixth Annual International Symposium on Fault-Tolerant Computing (FTCS '96)
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The authors deal with reconfiguration of a rectangular array of processors arranged as an N*N mesh, and a complete binary tree of N processors. They present new reconfiguration techniques that are modifications of the Diogenes approach proposed earlier by A.L. Rosenberg et al. (1983). These techniques reduce the overheads incurred in the earlier Diogenes schemes. Some of the previous approaches to the problem are summarized. Two schemes are presented for reconfiguring rectangular arrays and a scheme for reconfiguring trees. For the analysis of the different schemes presented, it is assumed that a processor has a square layout. These schemes are analyzed and their performance results are presented.