Configuration of VLSI Arrays in the Presence of Defects
Journal of the ACM (JACM)
An Efficient Unsorted VLSI Dictionary Machine
IEEE Transactions on Computers
Gracefully Degradable Processor Arrays
IEEE Transactions on Computers
A Fault-Tolerant Modular Architecture for Binary Trees
IEEE Transactions on Computers - The MIT Press scientific computation series
Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
A VLSI Implementation of the Simplex Algorithm
IEEE Transactions on Computers
A minimum area VLSI network for O(log n) time sorting
IEEE Transactions on Computers
Area-Time Optimal VLSI Networks for Computing Integer Multiplications and Discrete Fourier Transform
Proceedings of the 8th Colloquium on Automata, Languages and Programming
A VLSI tree machine for relational data bases
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Computational Aspects of VLSI
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The use of a fault-tolerant VLSI system for storing and solving linear programming problems is presented. The system can bear multiple faults in processing elements and/or links and still function with an acceptable performance degradation. It is based on an interconnection pattern consisting of a complete binary tree in which spare links between cousin nodes are added so as to reconfigure it as a ternary tree. At any given time of a computation, faulty processing elements and/or links are circumvented by using such spare links. It is shown that the total silicon area required by this structure is only a constant factor higher than that of a complete binary tree. The result is used to give an efficient implementation of the simplex algorithm in which the time required to perform a single pivot step matches a previously established lower bound for tree machines in spite of faults.